1. Field of the Invention
The present invention generally relates to lithography tools for the manufacture of integrated circuits (ICs) and, more particularly, to the alignment and stitching of fields in a lithographic exposure system where there are locations at which alignment marks have been omitted intentionally or cannot be located on the substrate.
2. Description of the Prior Art
Lithography systems have been used to expose patterns on semiconductor wafers in the fabrication of large-scale integrated (LSI) circuits. Unfortunately, many lithography tools have a field size limited to less than the largest IC chips to be written. This is inconvenient for device designers because they prefer not to expend the extra effort to subdivide chips into field size components. Therefore, it is useful to join or "stitch" fields with sufficient accuracy that the assembly appears essentially as one large field. This is increasingly a problem with very large scale integration (VLSI) and wafer scale integration (WSI).
Electron (E)-beam, ion beam and some optical steppers are examples of tools which must "stitch" fields together to expose the larger chips which will be required in the future. Prior techniques for stitching fields together in E-beam systems are described, for example, by Donald E. Davis in "Stitching Technique for Electron-Beam Lithography System", IBM Technical Disclosure Bulletin, vol. 21, no. 5, October, 1978, pp. 1875 and 1876, and in "Field Stitching Method", IBM Technical Disclosure Bulletin, vol. 22, no. 1, June, 1979, pp. 114 and 115. The first of these techniques takes advantage of the fact that image quality is primarily restricted to radial distance. Thus, if the field size is reconfigured to a small dimension in one axis, the other dimension can be expanded. Unfortunately, this technique is limited to chips which have their short dimension less than the square root of two times the maximum square chip. The second technique described by Davis takes advantage of the fact that image quality of the registration beam can be significantly degraded from that required for pattern writing without a serious impact on mark detection. By making a field range three times the writing range, marks at the chip perimeter can be detected and used to register the "writing quality" central portion of the field. The requirement for a deflection range one and a half times the chip size limits potential chip size and also degrades accuracy because deflection errors increase with range.
U.S. Pat. No. 4,489,241 to Matsuda et al. for "Exposure Method with Electron Beam Apparatus" and U.S. Pat. No. 4,789,945 to Niijima for "Method and Apparatus for Charged Particle Beam Exposure" disclose two other techniques for stitching fields. The Matsuda et al. technique divides areas of a wafer into sub sections for the purpose of reducing the volume of pattern information which must be contained in the tool memory at any instant and/or for the purpose of reducing the number of registration marks which must be scanned. While this technique eliminates some of the multi-field writing problems by adjusting for writing plane deviations via beam focus and repositioning the exposure field center based on height measurements; the block size and field size which can be used are restricted because in-field distortions are not well corrected. The Niijima technique divides a semiconductor chips into blocks and adjusts the block patterns based on marks in the four corners. Some of the four marks may be imaginary and are calculated from the real marks. This technique also does not correct for in-field errors caused by target plane errors and so is limited in accuracy or field size.
The following describes the problems in terms of an electron beam system; however, it will be understood that the situation is similar for other tools as well. In electron beam lithography, when the beam does not land perpendicular to the target, it will be displaced from its intended position when the height of the target is not nominal. Target heights generally vary due to manufacturing tolerances and distortions caused by hot processing. For an electron beam deflection with the apparent rocking point not at an infinite distance from the target the beam will land at an increasing angle from perpendicular as it is deflected which produces an increasing error. When the target is tilted and the corners of the fields are adjusted to match the desired positions by application of the usual linear corrections (i.e., A+Bx+Cy+Dxy), there will be an error at internal points which can be corrected by the addition of x.sup.2 and y.sup.2 terms.
There are three categories of problems. First, the axes of previous level patterns which are to be overlaid may be translated and/or rotated from the axes of the exposure tool. Second, the patterns may have some degree of distortion caused by the previous level of exposure, subsequent processing, or distortions of the writing tool. Third, the current exposure may have additional distortions of the exposure beam position over portions of the field.
In the single field/chip situation, errors due to the first category and the linear portion of the second category are typically corrected by detecting registration marks in a previous level pattern at the four corners of the field and "stretching" the current field to match the observed mark locations. Errors due to the third category are typically compensated by adjusting the field to correct for expected distortions. The magnitude of distortions can be extrapolated from corner errors, height information, and knowledge of deflection geometry. Registration marks in the interior of the chip are highly undesirable because they create forbidden areas which can not be used for circuits and devices and may disrupt the regularity of large area designs; therefore, four marks may not be available at the field corners to correct individual fields of a multi-field chip.